The following concept describes a simple yet viable solar grid tie inverter circuit which can be modified appropriately for generating wattage from 100 to 1000 VA and above.
What's a grid tie inverter? It's an inverter system designed to work just like an ordinary inverter using a DC input power with an exception that the output is fed back to the utility grid. This added power to the grid may be intended for contributing to the ever increasing power demands and also for generating a passive income from the utility company in accordance with their terms (applicable in limited countries only).
For implementing the above process, it's ensured that the output from the inverter is perfectly synchronized with grid power in terms of RMS, waveform, frequency and polarity, for preventing unnatural behavior and issues.
The proposed concept designed by me, is yet another grid tie inverter circuit (not verified) which is even simpler and reasonable than the previous design.
The circuit may be understood with the help of the following points:
AC mains from the grid system is applied to TR1 which is a stepped down transformer.
TR1 drops the mains input to 12V and rectifies it with the help of the bridge network formed by the four 1N4148 diodes.
The rectified voltage is used for powering the ICs via the individual 1N4148 diodes connected across the relevant pinouts of the ICs, while the associated 100uF capacitors make sure that the voltage is appropriately filtered.
The rectified voltage acquired just after the bridge is also used as the processing inputs for the two ICs.
Since the above signal (see the waveform image #1) is unfiltered it consists of a frequency of 100Hz and becomes the sample signal for processing and enabling the required synchronization.
First it's fed to pin#2 of IC555 where it's frequency is used for comparing with the sawtooth waves (see waveform #2) across pin#6/7 obtained from the collector of the transistor BC557.
The above comparison enables the IC to create the intended PWM output in sync with the frequency of the grid mains.
The signal from the bridge is also fed to pin#5 which fixes the RMS value of the output PWM precisely matching with the grid waveform (see waveform #3).
However at this point the output from the 555 is a low in power and needs to be boosted and also processed such that it replicates and generates both the halves of the AC signal.
For executing the above, the 4017 and the mosfet stage is incorporated.
The 100Hz/120Hz from the bridge is also received by the 4017 at its pin#14 which means now it's output would sequence and repeat from pin#3 back to pin#3 such that the mosfets are switched in tandem and exactly at the frequency of 50Hz, meaning each mosfet would conduct 50 times per second, alternately.
The mosfets respond to the above actions from the IC4017 and generate the corresponding push pull effect over the connected transformer which in turn produces the required AC mains voltage at its secondary winding. This may be implemented by supplying a DC input to the mosftes from a renewable source or a battery.
However the above voltage would be an ordinary square wave, not corresponding to the grid waveform, until and unless we include the network comprising the two 1N4148 diodes connected across the gates of the mosfets and pin#3 of IC555.
The above network chops the square waves at the gates of the mosftes accurately with respect to the PWM pattern or in other words it carves the square waves exactly matching the grid AC waveform, albeit in PWM form (see waveform #4).
The above output now is fed back to the grid conforming the grid specs and patterns accurately.
The power output can be altered right from 100 watts to 1000 watts or even more by appropriately dimensioning the input DC, the mosfets and the transformer ratings.
The discussed solar grid tie inverter circuit remains operative only so long as the grid power is present, the moment utility mains fails, TR1 switches OFF the input signals and the entire circuit comes to a halt, a situation that's strictly imperative for grid-tie inverter circuit systems.
Something's not right in the above design
According to Mr. Selim Yavuz the above design had a few things which looked doubtful and needed correction, let's hear what he had to say:
Hi Swag,
hope you're well.
I tried your circuit on a bread board. It seems to work except pwm part. For some reason, I get a double hump but no real pwm. Could you please help me understand how 555 does pwm? I noticed that 2.2k and 1u create a ramp of 10ms. I believe the ramp should be much faster than that as the half wave is 10ms. May be I missed a few things.
Also, 4017 does a clean job switching happily back and forth. When you power up, the 100 hz clock makes the counter always start from 0. How can we assure that it always in phase with the grid?
Appreciate your help and ideas.
Regards,
Selim
My Response to Mr. Selim
Hi Selim,
What's a grid tie inverter? It's an inverter system designed to work just like an ordinary inverter using a DC input power with an exception that the output is fed back to the utility grid. This added power to the grid may be intended for contributing to the ever increasing power demands and also for generating a passive income from the utility company in accordance with their terms (applicable in limited countries only).
For implementing the above process, it's ensured that the output from the inverter is perfectly synchronized with grid power in terms of RMS, waveform, frequency and polarity, for preventing unnatural behavior and issues.
The proposed concept designed by me, is yet another grid tie inverter circuit (not verified) which is even simpler and reasonable than the previous design.
The circuit may be understood with the help of the following points:
AC mains from the grid system is applied to TR1 which is a stepped down transformer.
TR1 drops the mains input to 12V and rectifies it with the help of the bridge network formed by the four 1N4148 diodes.
The rectified voltage is used for powering the ICs via the individual 1N4148 diodes connected across the relevant pinouts of the ICs, while the associated 100uF capacitors make sure that the voltage is appropriately filtered.
The rectified voltage acquired just after the bridge is also used as the processing inputs for the two ICs.
Since the above signal (see the waveform image #1) is unfiltered it consists of a frequency of 100Hz and becomes the sample signal for processing and enabling the required synchronization.
First it's fed to pin#2 of IC555 where it's frequency is used for comparing with the sawtooth waves (see waveform #2) across pin#6/7 obtained from the collector of the transistor BC557.
The above comparison enables the IC to create the intended PWM output in sync with the frequency of the grid mains.
The signal from the bridge is also fed to pin#5 which fixes the RMS value of the output PWM precisely matching with the grid waveform (see waveform #3).
However at this point the output from the 555 is a low in power and needs to be boosted and also processed such that it replicates and generates both the halves of the AC signal.
For executing the above, the 4017 and the mosfet stage is incorporated.
The 100Hz/120Hz from the bridge is also received by the 4017 at its pin#14 which means now it's output would sequence and repeat from pin#3 back to pin#3 such that the mosfets are switched in tandem and exactly at the frequency of 50Hz, meaning each mosfet would conduct 50 times per second, alternately.
The mosfets respond to the above actions from the IC4017 and generate the corresponding push pull effect over the connected transformer which in turn produces the required AC mains voltage at its secondary winding. This may be implemented by supplying a DC input to the mosftes from a renewable source or a battery.
However the above voltage would be an ordinary square wave, not corresponding to the grid waveform, until and unless we include the network comprising the two 1N4148 diodes connected across the gates of the mosfets and pin#3 of IC555.
The above network chops the square waves at the gates of the mosftes accurately with respect to the PWM pattern or in other words it carves the square waves exactly matching the grid AC waveform, albeit in PWM form (see waveform #4).
The above output now is fed back to the grid conforming the grid specs and patterns accurately.
The power output can be altered right from 100 watts to 1000 watts or even more by appropriately dimensioning the input DC, the mosfets and the transformer ratings.
The discussed solar grid tie inverter circuit remains operative only so long as the grid power is present, the moment utility mains fails, TR1 switches OFF the input signals and the entire circuit comes to a halt, a situation that's strictly imperative for grid-tie inverter circuit systems.
According to Mr. Selim Yavuz the above design had a few things which looked doubtful and needed correction, let's hear what he had to say:
Hi Swag,
hope you're well.
I tried your circuit on a bread board. It seems to work except pwm part. For some reason, I get a double hump but no real pwm. Could you please help me understand how 555 does pwm? I noticed that 2.2k and 1u create a ramp of 10ms. I believe the ramp should be much faster than that as the half wave is 10ms. May be I missed a few things.
Also, 4017 does a clean job switching happily back and forth. When you power up, the 100 hz clock makes the counter always start from 0. How can we assure that it always in phase with the grid?
Appreciate your help and ideas.
Regards,
Selim
My Response to Mr. Selim
Hi Selim,
Thanks for the update.
You are absolutely correct, the triangle waves should be much higher in frequency compared to the modulation input at pin#5.
For this we could go for a separate 2kHz 555 IC astable for feeding pin2 of the pwm IC 555.
This will solve all the issues according to me.
The 4017 should be clocked via 100Hz received from bridge rectifier and its pin3, pin2 should be used for driving the gates and pin4 connected to pin15. This will ensure perfect synchronization with the mains frequency.
Regards.
WARNING: THE IDEA IS BASED SOLELY ON IMAGINATIVE SIMULATION, VIEWER DISCRETION IS STRICTLY ADVISED.
The above GTI design seems to have missed a vital issue. As can be noticed the output from TR2 does not have a neutral, both the ends being "HOT" could cause serious problems when integrated to the grid.
The following diagram shows how this critical issue may be countered by using a single 1N5402 diode at the output. By introducing the diode we have forced the other terminal to become a "neutral" with respect to the other.
However, the above set up will only help to output half wave AC to the grid, nevertheless it will guarantee no short circuits or mismatch with the inverter integration.
For making the above design respond to both the half cycles, the following innovative alteration may be included in the output section of the proposed GTI circuit.
Here we have employed another step down transformer TR3 for triggering a couple n/p channels mosfets configured in a push-pull manner.
TR3s secondary terminals or the primary must be correctly checked and orientated so that the relevant mosfets connect the right "HOT" ends of TR2 corresponding to the positive/negative half cycles from the grid. Failing this could be fatal and cause a short circuit.
Q1/Q2 must be rated to handle 500V across their drain/source leads.
TR3 could be a 0-9V trafo
A major issue with the above design faced by many of the constructors was the heating up of one of the mosfets during the GTI operations. A possible cause and remedy as suggested by Mr. Hsen is presented below.
The proposed correction in the mosfet stage as recommended by Mr. Hsen is also enclosed here under, hopefully the said modifications will help control the issue permanently:
Hello mr. Swagatam: I watched again your diagram and I am firmly convinced that the gates of the MOSFETs will reach a modulating signal (HF PWM) and not a simple signal 50 cs, therefore I insist, must be incorporated a more powerful driver the CD4017, and the series resistance should be of a much lower value.
Another thing to consider is that at the junction of the resistor and the gate should not be another added element, and in this case I see going to the diodes 555. Because this may be the reason why one of the heats MOFETs because it can self oscillate.
So I think that the mosfet heats because it is oscillating and not because of the output transformer.
Excuse me, but my concern is that your project succeed because I feel very good and it is not my intention to criticize.
Yours affectionately, hsen
Finalized Design as per the above conversation
The above GTI design seems to have missed a vital issue. As can be noticed the output from TR2 does not have a neutral, both the ends being "HOT" could cause serious problems when integrated to the grid.
The following diagram shows how this critical issue may be countered by using a single 1N5402 diode at the output. By introducing the diode we have forced the other terminal to become a "neutral" with respect to the other.
However, the above set up will only help to output half wave AC to the grid, nevertheless it will guarantee no short circuits or mismatch with the inverter integration.
For making the above design respond to both the half cycles, the following innovative alteration may be included in the output section of the proposed GTI circuit.
Here we have employed another step down transformer TR3 for triggering a couple n/p channels mosfets configured in a push-pull manner.
TR3s secondary terminals or the primary must be correctly checked and orientated so that the relevant mosfets connect the right "HOT" ends of TR2 corresponding to the positive/negative half cycles from the grid. Failing this could be fatal and cause a short circuit.
Q1/Q2 must be rated to handle 500V across their drain/source leads.
TR3 could be a 0-9V trafo
A major issue with the above design faced by many of the constructors was the heating up of one of the mosfets during the GTI operations. A possible cause and remedy as suggested by Mr. Hsen is presented below.
The proposed correction in the mosfet stage as recommended by Mr. Hsen is also enclosed here under, hopefully the said modifications will help control the issue permanently:
Hello mr. Swagatam: I watched again your diagram and I am firmly convinced that the gates of the MOSFETs will reach a modulating signal (HF PWM) and not a simple signal 50 cs, therefore I insist, must be incorporated a more powerful driver the CD4017, and the series resistance should be of a much lower value.
Another thing to consider is that at the junction of the resistor and the gate should not be another added element, and in this case I see going to the diodes 555. Because this may be the reason why one of the heats MOFETs because it can self oscillate.
So I think that the mosfet heats because it is oscillating and not because of the output transformer.
Excuse me, but my concern is that your project succeed because I feel very good and it is not my intention to criticize.
Yours affectionately, hsen
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