The post discusses the pinout function and other important specifications of the IC 4043. Let's learn about the complete datasheet of this very interesting chip.
Pinout Datasheet of IC 4043
Technically the IC 4043 is a quad set/reset (R/S) latch with 3 logic state output.
To be more precise this chip has 4 sets of inputs (meaning 8 input pinouts) and 4 corresponding single outputs.
The 4 sets of inputs consist of 4 pairs of set/reset inputs.
For every set/reset we have one corresponding output.
All these set reset inputs respond to high logic signals, creating a bistable effect at their corresponding output pinouts.
Bistable refers to flip flop action, in other words a high pulse to the "set" input makes the corresponding output high from its original low state, and a high to the reset input reverts the above state from high back to low state.
Therefore basically to make a corresponding outputs high, we need to apply a high on their "set" inputs and to make the outputs low again we simply need to apply another high to their reset inputs.
The functioning of the input and output pinouts are as simple as that.
In addition to this, the IC has another interesting input pinout OE which is a common output enable pinout.
For enabling the above explained set/reset actions in the IC, this OE input should be connected with logic high or simply with Vdd (supply votage).
In the above situation the output is allowed with the specified flip flop functioning.
If the OE input is connected with ground, the output freezes and produces a high impedance response, that is neither shows a low output nor a high, rather locks input a unresponsive blocked state, hence the name 3 logic state output.
Thus the OE input can be used to shut down the IC functioning if required for a particular application.
The IC works best with supply voltages from 5 to 15V.
Let's summarize the input output pinout features and specifications of the IC 4043 with the following data:
1Q to 4Q (Pins: 2, 9, 10, 1) 3-state buffered latch output
1R to 4R (Pins: 3, 7, 11, 15) reset input (active HIGH)
1S to 4S (Pins: 4, 6, 12, 14) set input (active HIGH)
OE (Pin:5) common output enable input
VSS (Pin: 8) ground supply voltage
N.C. (Pin: 13) not connected
VDD (Pin: 16) supply voltage
Pinout Datasheet of IC 4043
Technically the IC 4043 is a quad set/reset (R/S) latch with 3 logic state output.
To be more precise this chip has 4 sets of inputs (meaning 8 input pinouts) and 4 corresponding single outputs.
The 4 sets of inputs consist of 4 pairs of set/reset inputs.
For every set/reset we have one corresponding output.
All these set reset inputs respond to high logic signals, creating a bistable effect at their corresponding output pinouts.
Bistable refers to flip flop action, in other words a high pulse to the "set" input makes the corresponding output high from its original low state, and a high to the reset input reverts the above state from high back to low state.
Therefore basically to make a corresponding outputs high, we need to apply a high on their "set" inputs and to make the outputs low again we simply need to apply another high to their reset inputs.
The functioning of the input and output pinouts are as simple as that.
In addition to this, the IC has another interesting input pinout OE which is a common output enable pinout.
For enabling the above explained set/reset actions in the IC, this OE input should be connected with logic high or simply with Vdd (supply votage).
In the above situation the output is allowed with the specified flip flop functioning.
If the OE input is connected with ground, the output freezes and produces a high impedance response, that is neither shows a low output nor a high, rather locks input a unresponsive blocked state, hence the name 3 logic state output.
Thus the OE input can be used to shut down the IC functioning if required for a particular application.
The IC works best with supply voltages from 5 to 15V.
Let's summarize the input output pinout features and specifications of the IC 4043 with the following data:
1Q to 4Q (Pins: 2, 9, 10, 1) 3-state buffered latch output
1R to 4R (Pins: 3, 7, 11, 15) reset input (active HIGH)
1S to 4S (Pins: 4, 6, 12, 14) set input (active HIGH)
OE (Pin:5) common output enable input
VSS (Pin: 8) ground supply voltage
N.C. (Pin: 13) not connected
VDD (Pin: 16) supply voltage
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